HPC-Enabled Path to Using, Scaling and Operating QC

This panel, moderated by Venkatesh Kannan (ICHEC), reverses the usual framing of quantum-HPC integration by asking how HPC can serve the scaling and operation of quantum computers. Mar Tejedor (BSC) describes Barcelona's setup of quantum devices alongside MareNostrum 5 and the multi-dimensional orchestration problem posed by differing qubit technologies, latencies, queues, and fidelity constraints. Sara Marzella (CINECA) stresses the value of HPC-hosted quantum emulators, including noise-aware emulation, for validating algorithms before consuming scarce QPU time, and notes the lack of realistic hybrid workloads for testing scheduling paradigms on systems such as Leonardo. Brendan Barry (Equal1) argues that classical compilation is now the bottleneck for hybrid variational algorithms, with routing and mapping costs exploding beyond a thousand qubits, and calls for HPC techniques such as GPU-accelerated and distributed compilers. Eric Mansfield (IQM) discusses controlling room-temperature electronics costs while qubit counts more than triple yearly, and using the LUMI system to simulate qubit physics. Nick Johnson (Riverlane) explains quantum error correction requirements, citing sub-10-microsecond latency for logical operations and microsecond-scale throughput, and describes the Delta Flow decoder stack and a benchmarking effort with Oak Ridge and Rigetti. The panel converges on the view that QEC needs dedicated tightly coupled hardware while application users need seamless abstractions, and that vendors and HPC centers must co-design integration without disrupting decades of established HPC practice.