Optimizing the Lifecycle: Performance, Efficiency, and Sustainability in HPC

This panel, moderated by Antonio Pena of the Barcelona Supercomputing Center, brings together Valerie Taylor (Argonne National Laboratory), Michele Weiland (EPCC, University of Edinburgh), Pedro Valero-Lara (Oak Ridge National Laboratory), and Miquel Pericas (Chalmers University of Technology) to debate performance, efficiency, and sustainability across the HPC lifecycle. Taylor argues for a holistic view of energy efficiency spanning algorithms, systems, architectures, and materials; Weiland calls for a whole-stack efficiency framework with standardized, transparent metrics, criticizing selective use of figures such as PUE and proposing data-center report cards modeled on home energy ratings. Valero-Lara examines how AI-driven hardware forces HPC to accommodate low and mixed precision while also offering AI as a tool to adapt the software stack, and Pericas advocates performance-portable programming models that expose energy-performance trade-offs through compilers and runtimes. Discussion topics include whether energy or power should become the primary optimization target, with Weiland insisting systems should be run at full utilization to maximize science throughput per embedded carbon; the difficulty of measuring power and attributing it to applications; data movement and the memory wall; over-provisioning in procurement; and the newly announced CPU-only Chinese system topping the TOP500 at roughly 20 megawatts per exaflop with 64-bit focus. The panel closes by emphasizing measurement tooling, energy per unit of science, user incentives, and AI-assisted energy optimization, while cautioning that sustainability should not reduce scientific output.