RESEARCH POSTER AWARD FINALIST: SpMV for the Cerebras Wafer-Scale Engine

In this research poster award finalist presentation, Jonathan Schaefer, a mathematics student and research assistant in the Future Computing Group at the High Performance Computing Center Stuttgart, presents an implementation of sparse matrix-vector multiplication (SpMV) for the Cerebras Wafer-Scale Engine. He explains the architecture's distinguishing features: a massive number of cores with distributed rather than unified memory, organized like an on-chip network where local memory access and nearest-neighbor communication each complete in a single clock cycle. The implementation uses a host-worker-device scheme in which a conventional Linux worker node performs the sophisticated preparation: slicing the sparse matrix, building compressed dot products that include only vector entries corresponding to nonzero matrix elements, packaging the data, and distributing it evenly to the device, which executes only local dot products before results are assembled back into the output vector. The evaluation yields three main lessons: the simple algorithm is communication bound; pre- and post-processing on the comparatively weak host contribute significantly to total runtime; and computation on the wafer-scale device itself is effectively free given its speed. Schaefer positions the work as a building block in two senses, as open-source code available on GitHub that others can integrate into Cerebras-based sparse workloads, and as a foundation for the group's ongoing research into more advanced sparse algorithms on wafer-scale hardware.