Route Wires, Not Packets: Revisiting On-Chip Interconnection Networks in the Era of A

This invited talk, delivered by Fabrizio Petrini of Intel Parallel Computing Labs (introduced by Jens Domke of RIKEN), argues for rethinking on-chip interconnection networks in the era of many metal layers. Petrini reframes Dally and Towles' influential 2001 paper 'Route Packets, Not Wires,' contending that its founding assumption of scarce top-level wiring no longer holds. Modern processes such as Intel 7, ASAP7, TSMC N3, and Intel 18A offer roughly 15 to 20 metal layers plus backside power delivery, freeing wiring resources. He presents two experiments. First, he characterizes wire propagation across metal layers on a reticle (about 35 by 25 mm), showing that thicker higher layers propagate signals faster and that corner-to-corner latency runs into tens of nanoseconds with repeaters. Second, using a network simulator with an 8x8 mesh under random traffic, he compares a conventional mesh network-on-chip against a wire-heavy crossbar. The mesh saturates near 30-40 percent injection with long-tailed, load- and location-dependent latencies, while the crossbar reaches roughly 90-100 percent with far more predictable, uniform behavior, delivering about 2.7x higher throughput. Petrini notes NoC area tax has grown from about 6 percent to 20-30 percent, stealing space from compute. He concludes that dedicated point-to-point wiring restores predictability, and points to photonics and 3D chiplet integration as complementary future directions.