Samsung Semiconductor Europe GmbH

In this vendor showdown segment moderated by Addison Snell of Intersect360 Research and Rupak Biswas of NASA Ames Research Center, Duke Nguyen of Samsung Semiconductor Europe presents Samsung's memory and storage roadmap for AI workloads. On the memory side, Samsung is producing HBM3E, with HBM4E planned for the following year and HBM5 in preparation for 2028. For storage, the upcoming PM1763 SSD targets AI servers with PCIe Gen 6 and TLC NAND, roughly doubling Gen 5 performance to about 28.4 GB/s sequential read and around 21 GB/s sequential write, with samples late in the year and mass production after; it is also designed for liquid-cooled systems in anticipation of air cooling becoming insufficient for AI power densities. A major theme is CXL: the first demonstrated application extends DRAM density for main memory, while the longer-term goal is a disaggregated memory pool, a box mixing DRAM and flash behind a switch that CPUs, GPUs, and DPUs can share dynamically to improve resource utilization in data centers, particularly for AI inference. In the question round, the speaker clarifies that Samsung's compute-storage positioning means high-performance, high-endurance NAND serving computation rather than processing inside the SSD; that Gen 6 drives will initially carry a price premium due to controller and NAND costs; and that liquid-cooling-friendly memory requires moving from vertical RDIMMs to horizontally mounted CAMM-style modules such as SOCAMM with LPDDR5X or later LPDDR6.