Scalable Network on Chips for the Chiplet Age

In this invited talk, Nils Burkardt, chief architect for on-chip networks at Extoll (a German company) and formerly part of the design team for the Extoll Tourmalet network card, addresses scalable network-on-chip (NoC) design for the chiplet age. He explains that AI and chiplets are reshaping the semiconductor landscape: monolithic dies are hitting lithography, mask, yield, and cost limits, driving a shift to smaller interconnected dies. He notes the chiplet market is expected to reach about 25 percent of designs by 2030 and that this requires rethinking system partitioning, advanced packaging, and die-to-die interfaces. Burkardt argues that classic crossbars lack routing resources in mature nodes, so meshes of cross points are used, and that tiling or stamping identical blocks reduces synthesis and place-and-route effort and physical congestion. A central theme is avoiding protocol translation: converting NoC packets to PCI Express or Ethernet to cross die boundaries costs latency, area, and power, so he advocates staying in the network domain using small controllers that add lightweight framing (such as CRC for reliability with retransmission) around native packets. This introduces a hierarchical network structure spanning dies that must remain deadlock- and livelock-free, using deterministic or adaptive routing. He compares PHY options, contrasting traditional SerDes (about 25 picojoules per bit, driving up to 50 centimeters) with the emerging UCIe standard designed for short die-to-die distances, achieving below 1.5 picojoules per bit and roughly one-third to one-fourth the macro area. Audience questions cover controller placement and I/O-die versus direct-gateway approaches.